1. Field of the Invention. This invention relates to data processing systems and, more particularly, to data processing systems having multiple processors with each processor having a cache connected thereto and a duplicate directory associated with a system controller.
2. Description of the Prior Art. A cache is a small, generally high speed memory store unit (cache memory) and a directory for locating the information within the cache memory. The cache memory is generally of a higher order of speed than the main memory. Thus, if the information is stored in the cache memory, quicker access by the processor to the required information is possible. Further, the cache memory is generally a small fraction of the size of the main memory. Operands and instructions, hereinafter generically referred to as information segments or data, are either fetched from the main memory and stored into the cache memory or they are loaded directly from the central processing unit (hereinafter referred to as CPU). When the CPU requires information segments, the cache memory is accessed first. If the information segments are not present in the cache memory, then they are obtained by accessing the main memory. The accessed information segments provided by the memory and transferred to the processor can be stored into the cache as they are passed through the CPU.
Generally it is desirable that the main memory contain all of the information segments and that the cache memory only reflects what is in the main memory. Thus, if a peripheral device requests and has transferred to it the contents of a portion of the memory, and further clears the information segments as they are provided from the main memory, it is possible that the cache of one or more of the processors could contain data which is no longer present in the main memory.
Further, it is possible that one of the processors writes an information segment into a particular storage location within the main memory. The cache of another processor can contain the information segment which has just been replaced by the first processor. Therefore, it is possible that if the processor accesses that particular information segment present in its cache memory, it could act upon data which is no longer identical with the information segment in the main memory.
One type of cache clearing operation is to clear the entire cache of all the processors any time data was written into the main memory or cleared by a peripheral device. However, in the usual case, the majority of the information segments stored within the cache are not outputted to the peripheral device and it is likely that information segments just cleared will have to be retrieved again from the main memory. This type of arrangement is shown in U.S. Pat. No. 3,845,474 issued to Lange et al on Oct. 29, 1974 and entitled "Cache Store Clearing Operation for Multiprocessor Mode".
Many data processing systems utilize segmentation and paging of the memory. Each segment is usually divided into smaller sections referred to as pages. The pages correspond to particular storage locations within the cache memory. Thus, it is possible to construct a device which provides selected clearing of only certain memory locations, i.e., those associated with a particular page, if that particular page is effected by an input/output operation or by another processor. This type of operation and apparatus is shown in U.S. Pat. No. 3,979,726 issued to Lange et al on Sept. 7, 1976 and entitled "Apparatus for Selectively Clearing a Cache Store in a Processor Having Segmentation and Paging". Although in this particular apparatus, the entire cache memory is not cleared, the fact does remain that useful data within the cache memory can be erased if the data relates to the page which is effected. It would therefore be necessary to access those information segments from the main memory under subsequent operations of the CPU.
Neither of these prior constructions shows a selective cache clearing utilizing a duplicate directory which communicates with the cache directory through the system controller.